1. Field of the Invention
The present invention relates to a method of manufacturing static random access memory (SRAM). More particularly, the present invention relates to a method of manufacturing buried contact in SRAM.
2. Description of Related Art
SRAM is one of the fastest operating semiconductor memory devices. Therefore, SRAM has been widely used, for example, in the cache memory of a computer. At present, SRAMs are also used in microcomputers, microprocessors and other digital equipment.
In general, an SRAM integrated circuit can be divided into two regions, namely, a memory cell region and a peripheral circuit region. The memory cell region comprises a large number of memory cell units, each for storing a single bit of data. The peripheral circuit region includes some address decoders for decoding the memory addresses coming from the memory cell region and some memory operating circuits. FIG. 1 is a circuit diagram of a memory unit in the memory cell region of an SRAM.
As shown in FIG. 1, an SRAM cell comprises resistors R.sub.1 and R.sub.2 and MOS transistors T.sub.1, T.sub.2, T.sub.3 and T.sub.4. The resistor R.sub.1 is connected in series with the MOS transistor T.sub.1, while the drain and the source of the MOS transistor T.sub.1 are connected to the voltage source V.sub.DD and ground V.sub.SS, respectively. Similarly, the resistor R.sub.2 is connected in series with the MOS transistor T.sub.2, while the drain and the source of the MOS transistor T.sub.2 are connected to the voltage source V.sub.DD and ground V.sub.SS, respectively.
In addition, the gate of the MOS transistor T.sub.2, the drain of MOS transistor T.sub.1 and the drain of MOS transistor T.sub.3 are connected at node point A. Similarly, the gate of the MOS transistor T.sub.1, the drain of MOS transistor T.sub.2 and the drain of MOS transistor T.sub.4 are connected at node point B. The gates of the MOS transistors T.sub.3 and T.sub.4 are connected to a word line WL, while the sources of the MOS transistor T.sub.3 and T.sub.4 are connected to the bit line BL and the complementary bit line BL, respectively. Transistors T.sub.1 and T.sub.2 act as drivers and transistors T.sub.3 and T.sub.4 act as a relays for accessing data. Lastly, the resistors R.sub.1 and R.sub.2 serve as loads.
In general, the contact of conventional SRAM is formed mostly above the source/drain regions. However, for integrated circuits having a high level of integration, the conventional method of forming contacts s becomes infeasible. Therefore, a type of contact known as a buried contact, which is especially suitable for forming local interconnects, is developed. A buried contact is capable of reducing wafer occupation. For example, when a buried contact is formed in an SRAM unit, as much as 25% of chip area can be saved. Hence, buried contact s are preferred in high-density semiconductor products.
FIGS. 2A through 2C are schematic, cross-sectional views showing the progression of steps in producing a buried contact in SRAM according to the conventional method.
First, as shown in FIG. 2A, a semiconductor substrate 10 is provided. Then, a device isolation structure, for example, a field oxide (FOX) layer 20 is formed above the substrate 10. Next, a gate oxide layer 30 is formed over the substrate 10, and then a first polysilicon layer 40 is deposited over the gate oxide layer 30. Thereafter, a photoresist layer 42 is coated over the first polysilicon layer 40, and then the photoresist layer 42 is patterned. In the subsequent step, the first polysilicon layer 40 and the gate oxide layer 30 are sequentially etched, thereby forming a buried contact opening 45.
Next, as shown in FIG. 2B, the photoresist layer 42 is removed. A second polysilicon layer 50 and a tungsten silicide layer 60 are sequentially formed over the first polysilicon layer 40 and the buried contact opening 45.
Next, as shown in FIG. 2C, conventional photolithographic technique is used to pattern out the source/drain region. Thereafter, the tungsten silicide layer 60 and the second polysilicon layer 50 are sequentially etched to form a conductive line 65 and a gate 75. Therefore, between the conductive line 65 and the gate 75, an opening 70 that exposes the surface of the source/drain region 90 is also formed. The opening 70 is purposely formed in a position slightly shifted towards the field oxide layer 20. Furthermore, since the second polysilicon layer 50 and the substrate 10 are made from the same material, a trench 80 as shown in FIG. 2C is also formed in the substrate 10. In addition, thickness of gate oxide layer 30d underneath the opening 70 is also reduced due to etching.
Thereafter, ions are implanted into the substrate at the bottom of the opening 70 using the tungsten silicide layer 60 as a mask, thereby forming doped regions (source/drain region) 90 and (buried contact) 100 in the substrate. Since the ions need not strike the substrate perpendicularly, and a trench 80 is formed in a previous etching operation, some ions will be trapped in the buried contact 100 on the left side at the bottom of the opening 70 aside from the source/drain region 90.
In the aforementioned method of forming an opening 70 to the source/drain region 90, a trench 80 is also formed. If the depth of this trench 80 is great, contact area between the buried contact 100 and the source/drain region 90 will be small. Hence, resistance at the junction will increase considerably. Moreover, if the depth of the trench 80 is too deep, there may be re-direction of current. Instead of passing through the implanted regions 90 and 100, the current flows by way of the substrate 10 and ground, thereby leading to junction leakage.
In light of the foregoing, there is a need a more efficient method of fabrication buried contact in SRAM.